An Active Cancellation Architecture for High-speed Track-and-Hold Amplifiers in 45nm CMOS SOI
نویسندگان
چکیده
This paper presents a 40GS/s track-and-hold amplifier with active cancellation. An active cancellation circuitry was implemented to mitigate the leakage caused by the parasitic capacitance of the sampling transistor. The cancellation technique increases the isolation between the track and hold modes, especially at high input frequencies. An SFDR3 of 62dB was measured for 5GHz input signal sampled at 40GS/s. A droop voltage of 20μv/ns was recorded. The chip was fabricated in IBM 45nm CMOS SOI technology node.
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